모집분야 |
SoC Design & Verification |
자격요건 |
학력 : 대학교 졸업(4년) 이상 |
경력 : 동일 직종 3년 이상 경력 |
담당업무 |
IP / SOC RTL Verification |
IP level RTL Design |
SOC RTL Integration Design |
필수사항 |
IP or SOC RTL Design with Verilog-HDL(over 3 years) |
IP or SOC RTL Verification(over 3 years) |
Cadence/Synopsys simulator tool experience |
우대사항 |
Systemverilog based Design or Verification |
UVM based Verification & Coverage for IP or SOC Level |
UVM based Verification Environment Setup |
Synopsys/Cadence UVM based VIP Verification Integration |
MCU/CPU based Design/Verification |
Magillem design integration tool |
Top Design RTL integration |
Design Synthesis/Formal/DFT/SDC |