1. Senior Physical Designer Engineer
 
  - 4년제 대졸이상, 석사 우대
 - 반도체 설계 경력 10년이상
 -  Chip Top 경험:  Hierarchy Design 경험 ( Over 10 Blocks) , Block Partition, Top CTS, STA
  -  P&R 경험: Floorplan, Place & Route, CTS, STA, DRC/LVS, IR Drop
    (ICC or Innovus, Prime-Time, StarRC, ICV or Calibre, RedHawk)
-  TSMC 16nm/12nm or Samsung 14nm 이하 경험자 우대
 
 2. Junior Physical Designer Engineer
 
  - 4년제 대졸이상, 석사 우대
 -  반도체 설계 경력 3년이상
  - P&R 경험: Floorplan, Place & Route, CTS, STA, DRC/LVS, IR Drop
    (ICC or Innovus, Prime-Time, StarRC, ICV or Calibre, RedHawk)
  -  TSMC 16nm/12nm or Samsung 14nm 이하 경험자 우대
 
 3. IR Drop/EM Analysis Engineer
 
 - 4년제 대졸 이상, 석사 우대
 - 반도체 설계 경험 5년 이상
 
 
4. PI(Physical Implementation) Engineers
다음 각 분야 전문 인력
- DFT Implementation
- SCAN insertion / ATPG / Scan Simulation (Test Compiler / TetraMax)
- BIST/BIRA Insertion & Simulation : Tessent MBIST / JTAG / IJTAG
- SDC Creation & Clean
- Spyglass LINT/SDC/DFT Check
- Logic Synthesis : DC/DCT/DCG
- Equivalence Check : Formality/Conformal
- LDRC : Logic Design Rule Check (Spyglass_LDRC)
- STA (Static Timing Analysis)
- Timing Closure : cross-talk/noise/mttv/setup/hold fix (Prime_Time, Physical-aware ECO)
- Low Power Design : UPF Creation & Low power Rule Check(VC_LP)
- Power Analysis : Vectored / Vectorless (PTPX)
- Implementation 자동화Platform 개발
- Simulator & Debugger : VCS / NC-verilog / Verdi